MCF5206ECFT40

Product Summary

The MCF5206ECFT40 is an integrated microprocessor. It combines a ColdFire core with several peripheral functions such as a DRAM controller, timers, parallel and serial interfaces, and system integration. This device MCF5206ECFT40 is an enhanced version of the MCF5206, which is in production today. Not only does the MCF5206ECFT40 provide a performance upgrade to the MCF5206 due to the increased 4-Kbyte I-cache, 8-Kbyte SRAM and increased frequency, but this device MCF5206ECFT40 also integrates an additional multiply accumulate (MAC) unit, hardware divide, and two-channel DMA to the device while maintaining pin compatibility with the MCF5206.

Parametrics

MCF5206ECFT40 absolute maximum ratings: (1)RAM Size: 8K x 8; (2)Number of I /O: 8; (3)Package / Case: 160-BQFP; (4)Speed: 40MHz; (5)Oscillator Type: External; (6)Packaging: Tray; (7)Program Memory Type: ROMless; (8)Core Processor Coldfire: V2; (9)Core Size: 32-Bit; (10)Operating Temperature: -40 to 85℃; (11)Connectivity: EBI/EMI, I²C, UART/USART; (12)Peripherals: DMA, WDT; (13)Voltage - Supply (Vcc/Vdd): 3 V ~ 3.6 V; (14)Lead Free Status: Contains Lead; (15)RoHS Status: RoHS Non-Compliant.

Features

MCF5206ECFT40 features: (1)Multiply accumulate; (2)High speed, complex arithmetic functions for signal processing applications; (3)Single clock issue rate with 3-stage execution pipeline; (4)One MAC cycle for 16x16 and 32x32 multiplies, all with 32-bit accumulate; (5)Four-Kbyte direct-mapped instruction cache ; (6)Eight-Kbyte on-chip SRAM that provides one-cycle access to critical code and data; (7)DRAM controller; (8)Programmable refresh timer provides CAS before RAS refresh; (9)Support for 2 separate memory banks; (10)Support for fast page mode DRAMs and extended-data-out (EDO) DRAMs; (11)External bus master access; (12)DMA controller; (13)Two fully programmable channels with external request pins supporting dual-address and single address transfers with 32-bit capability; (14)Two address pointers per channel that can increment or remain constant; (15)16-bit transfer counter per channel; (16)Operand packing and unpacking; (17)Auto-alignment transfers for efficient block movement; (18)Bursting and cycle stealing; (19)Two clock-cycle internal access.

Diagrams